A flash memory cell has a transistor structure containing a floating gate electrode and a control gate electrode, which are isolated from the semiconductor material and from one another in each case by thin layers of a dielectric. When a suitable voltage is applied to the control gate electrode, charge carriers tunnel from the channel region of the transistor through the thin dielectric onto the floating gate electrode, as a result of which the memory cell is programmed. Since the threshold voltage of the transistor changes by virtue of the charge carriers on the floating gate electrode, the programmed state can be distinguished from the original state, i.e. the cell can be read. During the erasure process, the charge is removed from the floating gate electrode by oppositely applied potentials, so that the original (uncharged) state of the memory transistor is attained again, at least approximately. In the case of previous flash memory cells there are problems with the miniaturization of the transistors since the thickness of the tunnel oxide between the semiconductor material and the floating gate electrode cannot be reduced below 8 nm for reasons of adequate data retention. A scaled miniaturization of this transistor with the thickness of the gate oxide remaining the same is not possible.